The system and method disclosed herein relate to generating a field effect transistor (FET) corner model and, more particularly, to generating a FET corner model that preserves the partial correlations between statistical model parameters (e.g., channel lengths, threshold voltages, overlap capacitances, channel widths, etc.) of different types of FETs within an integrated circuit.
Typically, partial correlations exist between certain statistical model parameters (e.g., channel lengths, threshold voltages, overlap capacitances, channel widths, etc.) of different types of field effect transistors (e.g., a low threshold voltage n-type field effect transistor (LVT nFET), a low threshold voltage p-type field effect transistor (LVT pFET), a regular threshold voltage n-type field effect transistor (RVT nFET), a regular threshold voltage p-type field effect transistor (RVT pFET), a high threshold voltage n-type field effect transistor (HVT nFET), a high threshold voltage p-type field effect transistor (HVT pFET), etc.) with regard to performance (e.g., delay of logic gates) within the same integrated circuit. Those skilled in the art will recognize that a “partial correlation” is a measurable degree of association between two otherwise random variables. It would be advantageous to be able to generate a FET corner model that accurately preserves these partial correlations without requiring a significant number (e.g., hundreds, thousands or tens of thousands) of simulations.